1. Field of the Invention
The invention relates generally to insulating layers formed between conductors in integrated circuits, and more particularly to the formation of fluorinated low-k dielectric materials.
2. Background
Advances in semiconductor manufacturing technology have led to the integration of tens, and more recently hundreds, of millions of circuit elements, such as transistors, on a single integrated circuit (IC). To achieve such dramatic increases in the density of circuit components has required semiconductor manufacturers to scale down the physical dimensions of the circuit elements, as well as the interconnection structures used to connect the circuit elements into functional circuitry.
One consequence of scaling down the physical dimensions of circuit elements has been to reduce the spacing between interconnect lines. Interconnect lines on integrated circuits are used for power and signal distribution. A dielectric material is typically disposed between the various interconnect lines on integrated circuits. Because capacitance between two conductors is a function of the spacing between those conductors, the parasitic capacitance increases as the conductors are formed closer together. It is well known that increased parasitic capacitance between signal conductors on an integrated circuit can have adverse effects such as increased power consumption, speed degradation, and signal cross-talk. One approach to reducing this parasitic capacitance is to provide dielectric materials between the interconnect lines where those dielectric materials have reduced dielectric constants.
Fluorinated dielectric materials tend to have lower dielectric constants than their unfluorinated counterparts. For example, the fluorinated oxide of silicon, SiOF, has a dielectric constant of approximately 3.6, whereas the unfluorinated silicon dioxide, SiO2, has a dielectric constant of approximately 4. Similarly, fluorinating various organic dielectric materials can also reduce their corresponding dielectric constants. For example, a dielectric constant of approximately 2.4 is obtained for the fluorinated organic dielectric parylene-AF4.
Unfortunately, integration of fluorinated dielectric materials into microelectronic components has presented many serious reliability issues related to the reaction of fluorine with surrounding materials. These reactions have been found to result in blistering and in delamination. FIG. 1 shows a cross-section of a portion of an integrated circuit having a patterned layer of fluorinated dielectric. Patterned fluorinated dielectric 104 is disposed over a substrate 102. A material 110 is deposited over the patterned fluorinated dielectric 104. FIG. 1 further shows a blister 108 and a delamination 106. Both blistering and delamination are undesirable physical deformations in integrated circuits that adversely affect their reliability.
What is needed are dielectric materials having reduced dielectric constants that are suitable for integration into microelectronic components.